1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices with interconnect opening and more particularly to the fabrication of a interconnect opening using hardmasks and dielectric layers and etch processes.
2) Description of the Prior Art
As integration density of an integrated circuit device increases, the size of a semiconductor device and interconnection lines thereon becomes smaller and smaller. In order to build more semiconductor devices in a given cell plane with reduced area, three-dimensional semiconductor devices and interconnection lines are being employed. A three-dimensional interconnection line is typically shown in multi-level metallization. Multi-level metallization is carried out as a post-process after a preprocess such as forming a transistor, forming a capacitor and forming a bit line.
Current methods for forming via contact opening in low k materials using hardmask need to be improved.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
U.S. Pat. No. 6,812,131: Kennedy—Use of sacrificial inorganic dielectrics for dual damascene processes utilizing organic intermetal dielectrics—Production of conducting vias and conducting lines for integrated circuits in semiconductor devices, comprises depositing sacrificial inorganic dielectric in via opening to fill via opening and cover top surface of stack.
US2004014711A1: Huang et al.—Polycarbosilane buried etch stops in interconnect structures—Interconnect structure useful in integrated circuits and microelectronic devices comprises a buried etch stop layer containing a polymeric material, a via level interlayer dielectric.
US20030232504A1: Eppler et al.—Process for etching dielectric films with improved resist and/or etch profile characteristics—Dielectric layer etching for integrated circuit production, involves setting ratio of silane gas to fluorocarbon gas and ratio of hydrogen gas to fluorocarbon gas in etchant gas, to specific range.
U.S. Pat. No. 6,184,142: Chung et al.—Process for low k organic dielectric film etch—Etching of an organic film having low dielectric constant, for use as an interlevel dielectric film, by etching using hardmask layer as mask to transfer the pattern into the low dielectric constant organic layer